SF Tensor
Infrastructure for AI labs to focus on research.
What SF Tensor does
AI researchers should be pushing the boundaries of what's possible with new architectures and training methods. Instead, they waste weeks configuring cloud infrastructure, debugging distributed systems, and optimizing their GPU code. We know because we lived it: While training our own models across thousands of GPUs earlier this year, we spent more time fighting our infrastructure than doing actual research. That's why we're building two things. First, Elastic Cloud: a managed platform that automatically finds the cheapest GPUs across all providers, handles spot instance preemption, and cuts compute costs by up to 80%. Second, automatic kernel optimization that makes training code run faster by modeling hardware topology, often beating hand-tuned implementations. The problem is that getting high performance across different hardware is genuinely hard. NVIDIA's CUDA moat exists because writing fast kernels requires deep expertise. Most teams either accept vendor lock-in or hire expensive kernel engineers. Our goal is to break the CUDA moat. The compute bottleneck is the biggest constraint on AI progress. NVIDIA can't manufacture enough GPUs, and their monopoly keeps prices astronomical. Meanwhile, AMD, Google, and Amazon are shipping capable alternative hardware that nobody uses because the software is too hard. We're breaking that moat. If we succeed, anyone will be able to train state-of-the-art models without thinking past their PyTorch code.
4 open roles
What the role involves
About SF Tensor At The San Francisco Tensor Company, we believe the future of AI and high-performance computing depends on rethinking the entire software and infrastructure stack. Today's developers face bottlenecks across hardware, cloud, and code optimization that slow progress before ideas can reach their full potential. Our mission is to remove those barriers and make compute faster, cheaper, and universally portable. We are building a Kernel Optimizer that automatically transforms code into its most efficient form, combined with Tensor Cloud for adaptive, cross-cloud compute and Emma Lang, a new programming language for high-performance, hardware-aware computation. Together, these technologies reinvent the foundations of AI and HPC. SF Tensor is proudly backed by Susa Ventures and Y Combinator, as well as a group of angels including Max Mullen and Paul Graham as well as founders and executives of NeuraLink, Notion and AMD. We are partnering with researchers, engineers, and organizations who share our belief that the next breakthroughs in AI require breakthroughs in compute. About the Role We're hiring a Founding GPU Compiler Engineer to build the core compilation infrastructure for our AI compiler. That means taking models from PyTorch, JAX, and TensorFlow and turning them into highly optimized binaries for large-scale AI pre-training. You'll own the entire compiler stack, from ingesting StableHLO all the way to backend code generation, and you'll work across targets like NVIDIA, AMD, Trainium, and TPU. You'll help shape our architecture, tooling, and overall engineering culture from the very beginning. What You'll Do Design and implement the main compilation pipeline, from StableHLO to executable GPU and host binaries Build and extend MLIR dialects and passes to optimize AI workloads Develop backend code generation for multiple targets (NVIDIA PTX/SASS, AMD GCN/RDNA, Trainium, TPU) Implement classic compiler optimizations customized for large-scale training (fusion, tiling, memory planning, scheduling) Build search-based compiler infrastructure to explore different optimization options Create hybrid codegen paths for cases where direct MLIR lowering isn't practical Set up testing, benchmarking, and performance regression systems Work closely with ML researchers to understand workload characteristics and find optimization opportunities What We're Looking For Deep experience with compiler infrastructure (LLVM, MLIR, or similar) Strong background in GPU architecture and low-level optimization (CUDA, ROCm, or equivalent) Hands-on experience with at least one of: PTX/SASS, GCN/RDNA assembly, or other GPU ISAs Familiarity with ML compiler stacks (XLA, TVM, Triton, torch.compile, or similar) Solid systems programming skills in C++ and/or Rust Proven track record of building production-grade compiler infrastructure Nice to Have Background in distributed systems or multi-device compilation Contributions to open-source compiler projects Experience with autotuning or search-based optimization Familiarity with large-scale training infrastructure Experience with (Stable)HLO Why Join Us You'll be one of the first engineers defining how we compile and optimize AI workloads. It's a rare chance to build a compiler stack from the ground up, with a direct impact on the efficiency of large-scale AI training. We believe in the power of in-person collaboration to solve the hardest problems and foster a strong team culture. We offer relocation assistance and look forward to you joining us in our San Francisco office. The base salary range for this full-time position is $285,000 - $315,000 + bonus + equity + benefits.
What the role involves
About SF Tensor At The San Francisco Tensor Company, we believe the future of AI and high-performance computing depends on rethinking the entire software and infrastructure stack. Today's developers face bottlenecks across hardware, cloud, and code optimization that slow progress before ideas can reach their full potential. Our mission is to remove those barriers and make compute faster, cheaper, and universally portable. We are building a Kernel Optimizer that automatically transforms code into its most efficient form, combined with Tensor Cloud for adaptive, cross-cloud compute and Emma Lang, a new programming language for high-performance, hardware-aware computation. Together, these technologies reinvent the foundations of AI and HPC. SF Tensor is proudly backed by Susa Ventures and Y Combinator, as well as a group of angels including Max Mullen and Paul Graham as well as founders and executives of NeuraLink, Notion and AMD. We are partnering with researchers, engineers, and organizations who share our belief that the next breakthroughs in AI require breakthroughs in compute. About the Role We're looking for a Founding GPU Kernel Engineer who lives right at the boundary between hardware and software. Someone who thinks in warps, occupancy, and memory hierarchies, and can squeeze every last FLOP out of a GPU. Your job is to go deeper than anyone else. You'll hand-tune kernels to figure out what's actually possible on the hardware, and then turn that knowledge into compiler optimization passes that help every model we compile. What You'll Do Write and hand-optimize GPU kernels for ML workloads (matmuls, attention, normalization, etc.) to set the performance ceilings Profile at the microarchitectural level: look into SM utilization, warp stalls, memory bank conflicts, register pressure, instruction throughput Debug performance issues by digging deep into things like clock speeds, thermal throttling, driver behavior, hardware errata Turn your hand-optimization insights into automated compiler passes (working closely with our compiler team) Develop performance models that predict how kernels will behave across different GPU architectures Build tools and methods for systematic kernel optimization Work with NVIDIA, AMD, and emerging AI accelerators - understand the common parts and what's vendor-specific What We're Looking For Deep expertise in GPU architecture Proven track record of hand-writing kernels that match or beat vendor libraries (cuBLAS, cuDNN, CUTLASS) Strong skills with low-level profiling tools: Nsight Compute, Nsight Systems, rocprof, or equivalents Experience reading and reasoning about PTX/SASS or GPU assembly Solid systems programming in C++ and CUDA (or ROCm/HIP) Good understanding of how high-level ML operations map to hardware execution Experience with distributed training systems: collective ops like all-reduce and all-gather, NCCL/RCCL, multi-node communication patterns Nice to Have HPC background: experience with large-scale scientific computing, MPI, or work in supercomputing Background in electrical engineering, computer architecture, or hardware design Driver development experience (NVIDIA, AMD, or other accelerators) Experience with MLIR, LLVM, or compiler backends Deep knowledge of distributed ML training: gradient accumulation, activation checkpointing, pipeline/tensor parallelism, ZeRO-style optimizations Familiarity with custom accelerators: TPUs, Trainium, Inferentia, or similar Knowledge of high-speed interconnects: NVLink, NVSwitch, InfiniBand, RoCE Publications or contributions in GPU optimization, HPC, or ML systems Experience at NVIDIA, AMD, a national lab, or an AI hardware/infrastructure company Why Join Us This role is for someone who wants to know why things are fast or slow on the hardware. You'll have a direct impact on the performance of large-scale AI training, tackling problems that need real depth. If you've ever been annoyed that y
What the role involves
About SF Tensor At The San Francisco Tensor Company, we believe the future of AI and high-performance computing depends on rethinking the entire software and infrastructure stack. Today's developers face bottlenecks across hardware, cloud, and code optimization that slow progress before ideas can reach their full potential. Our mission is to remove those barriers and make compute faster, cheaper, and universally portable. We are building a Kernel Optimizer that automatically transforms code into its most efficient form, combined with Tensor Cloud for adaptive, cross-cloud compute and Emma Lang, a new programming language for high-performance, hardware-aware computation. Together, these technologies reinvent the foundations of AI and HPC. SF Tensor is proudly backed by Susa Ventures and Y Combinator, as well as a group of angels including Max Mullen and Paul Graham as well as founders and executives of NeuraLink, Notion and AMD. We are partnering with researchers, engineers, and organizations who share our belief that the next breakthroughs in AI require breakthroughs in compute. About the Role We're building a next-generation AI compiler that uses machine learning to optimize machine learning. As a Founding Research Engineer focused on AI-driven compilation, you'll develop the agentic and reinforcement learning systems that guide our compiler's optimization decisions. This is a research-heavy role right at the intersection of compilers and ML. You'll design learned systems that can explore huge optimization spaces, discover new code transformations, and keep improving compilation quality over time. What You'll Do Design and implement RL-based systems for compiler optimization (things like phase ordering, tile size selection, scheduling decisions, and fusion strategies) Build agentic compilation systems that use LLMs to reason about code and apply transformations Develop reward models and the training infrastructure for our compiler optimization agents Create representations and embeddings of compiler IR that work well for learned optimization Design feedback loops that let the system improve continuously from real production workloads Work closely with compiler engineers to integrate these learned components into the full compilation pipeline Run experiments, dig into the results, and iterate on what works Publish and open-source research when it makes sense What We're Looking For Strong background in reinforcement learning, with hands-on experience training RL agents on real problems Experience building LLM agents, tool use, or other agentic systems Good familiarity with GPU programming concepts Solid proficiency in Python and PyTorch or JAX Ability to design and run solid, rigorous experiments Nice to Have Experience with ML compiler stacks (XLA, TVM, Triton, MLIR) Experience with RLHF, reward modeling, or preference learning Background in combinatorial optimization or program synthesis Publications or clear research contributions in RL, learned optimization, or ML for systems Familiarity with compiler concepts (IR, optimization passes, code generation) Familiarity with GPU performance optimization Prior work on learned indexing, learned query optimization, or similar ML-for-systems projects Why Join Us Compiler optimization is one of the most exciting areas for applying learned systems. There are massive action spaces, clear reward signals, and huge real-world impact. You'll get the freedom to chase ambitious research ideas while building things that actually ship to production. We believe in the power of in-person collaboration to solve the hardest problems and foster a strong team culture. We offer relocation assistance and look forward to you joining us in our San Francisco office. The base salary range for this full-time position is $275,000 - $315,000 + bonus + equity + benefits.
What the role involves
About SF Tensor At The San Francisco Tensor Company, we believe the future of AI and high-performance computing depends on rethinking the entire software and infrastructure stack. Today's developers face bottlenecks across hardware, cloud, and code optimization that slow progress before ideas can reach their full potential. Our mission is to remove those barriers and make compute faster, cheaper, and universally portable. We are building a Kernel Optimizer that automatically transforms code into its most efficient form, combined with Tensor Cloud for adaptive, cross-cloud compute and Emma Lang, a new programming language for high-performance, hardware-aware computation. Together, these technologies reinvent the foundations of AI and HPC. SF Tensor is proudly backed by Susa Ventures and Y Combinator, as well as a group of angels including Max Mullen and Paul Graham as well as founders and executives of NeuraLink, Notion and AMD. We are partnering with researchers, engineers, and organizations who share our belief that the next breakthroughs in AI require breakthroughs in compute. About the Role We're searching for a Founding Product Engineer who'll own the entire user-facing surface of our training platform: everything from the daily interfaces our users interact with to the systems that make it all run. This role requires taking vague features and shipping them from start to finish. We care just as much about how the product feels to use as whether it technically works. If you're someone who gets genuinely annoyed by janky animations, sloppy spacing, or interactions that feel off, we'd love to talk. What You'll Do Take full ownership of product areas: scoping, designing, building, and iterating on them Build clean, fast, polished web interfaces with Next.js that feel almost native Write simple, performant backend services in Bun/TypeScript Deploy and manage infrastructure on AWS (EKS, S3, and the usual suspects) using Kubernetes Obsess over the small things, from loading states, smooth animations, solid error handling to edge cases, the things that turn a good product into a great one Make smart product tradeoffs with little hand-holding: know when to ship fast and when to spend extra time polishing Help shape our product culture and engineering standards as one of the first engineers on the team What We're Looking For Proven experience shipping complete products, not just individual features (ideally something you can show us) Serious frontend skills: you're very comfortable with React/Next.js, CSS, and modern web APIs A sharp eye for design and motion: you notice when an animation eases awkwardly, when padding feels inconsistent, or when something just looks cheap Solid backend chops: you can build APIs, work with databases, and troubleshoot production issues Enough infrastructure comfort to handle AWS, containers, and Kubernetes (you don't need to be a DevOps wizard, but you're not scared of a Dockerfile either) Ability to move independently in ambiguous situations Real taste. You have strong opinions (and reasons) about what makes software feel good to use Nice to Have Experience with Bun, or eagerness to dive in Background in developer tools, infrastructure products, or building for technical users Familiarity with Cloudflare (Workers, R2, etc.) Time spent at early-stage startups or as an early employee Open-source contributions or a public portfolio you're proud of Comfort using design tools like Figma to mock things up yourself when needed Why Join Us You'd be one of the first product engineers building tools that will change how people train AI models at scale. If you want to work on something that actually matters and have the freedom to build it the right way, this is the spot. We believe in the power of in-person collaboration to solve the hardest problems and foster a strong team culture. We offer relocation assistance and look forward to you joining us in our San Franc
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Company facts compiled from public sources and last refreshed 9 September 2026. Details change; treat the company’s own site as the authority.