What the role involves
About SF Tensor
At The San Francisco Tensor Company, we believe the future of AI and high-performance computing depends on rethinking the entire software and infrastructure stack. Today's developers face bottlenecks across hardware, cloud, and code optimization that slow progress before ideas can reach their full potential. Our mission is to remove those barriers and make compute faster, cheaper, and universally portable.
We are building a Kernel Optimizer that automatically transforms code into its most efficient form, combined with Tensor Cloud for adaptive, cross-cloud compute and Emma Lang, a new programming language for high-performance, hardware-aware computation. Together, these technologies reinvent the foundations of AI and HPC.
SF Tensor is proudly backed by Susa Ventures and Y Combinator, as well as a group of angels including Max Mullen and Paul Graham as well as founders and executives of NeuraLink, Notion and AMD. We are partnering with researchers, engineers, and organizations who share our belief that the next breakthroughs in AI require breakthroughs in compute.
About the Role
We're building a next-generation AI compiler that uses machine learning to optimize machine learning. As a Founding Research Engineer focused on AI-driven compilation, you'll develop the agentic and reinforcement learning systems that guide our compiler's optimization decisions.
This is a research-heavy role right at the intersection of compilers and ML. You'll design learned systems that can explore huge optimization spaces, discover new code transformations, and keep improving compilation quality over time.
What You'll Do
Design and implement RL-based systems for compiler optimization (things like phase ordering, tile size selection, scheduling decisions, and fusion strategies)
Build agentic compilation systems that use LLMs to reason about code and apply transformations
Develop reward models and the training infrastructure for our compiler optimization agents
Create representations and embeddings of compiler IR that work well for learned optimization
Design feedback loops that let the system improve continuously from real production workloads
Work closely with compiler engineers to integrate these learned components into the full compilation pipeline
Run experiments, dig into the results, and iterate on what works
Publish and open-source research when it makes sense
What We're Looking For
Strong background in reinforcement learning, with hands-on experience training RL agents on real problems
Experience building LLM agents, tool use, or other agentic systems
Good familiarity with GPU programming concepts
Solid proficiency in Python and PyTorch or JAX
Ability to design and run solid, rigorous experiments
Nice to Have
Experience with ML compiler stacks (XLA, TVM, Triton, MLIR)
Experience with RLHF, reward modeling, or preference learning
Background in combinatorial optimization or program synthesis
Publications or clear research contributions in RL, learned optimization, or ML for systems
Familiarity with compiler concepts (IR, optimization passes, code generation)
Familiarity with GPU performance optimization
Prior work on learned indexing, learned query optimization, or similar ML-for-systems projects
Why Join Us
Compiler optimization is one of the most exciting areas for applying learned systems. There are massive action spaces, clear reward signals, and huge real-world impact. You'll get the freedom to chase ambitious research ideas while building things that actually ship to production.
We believe in the power of in-person collaboration to solve the hardest problems and foster a strong team culture. We offer relocation assistance and look forward to you joining us in our San Francisco office.
The base salary range for this full-time position is $275,000 - $315,000 + bonus + equity + benefits.
What they ask for
About SF Tensor
AI researchers should be pushing the boundaries of what's possible with new architectures and training methods. Instead, they waste weeks configuring cloud infrastructure, debugging distributed systems, and optimizing their GPU code. We know because we lived it: While training our own models across thousands of GPUs earlier this year, we spent more time fighting our infrastructure than doing actual research. That's why we're building two things. First, Elastic Cloud: a managed platform that automatically finds the cheapest GPUs across all providers, handles spot instance preemption, and cuts compute costs by up to 80%. Second, automatic kernel optimization that makes training code run faster by modeling hardware topology, often beating hand-tuned implementations. The problem is that getting high performance across different hardware is genuinely hard. NVIDIA's CUDA moat exists because writing fast kernels requires deep expertise. Most teams either accept vendor lock-in or hire expensive kernel engineers. Our goal is to break the CUDA moat. The compute bottleneck is the biggest constraint on AI progress. NVIDIA can't manufacture enough GPUs, and their monopoly keeps prices astronomical. Meanwhile, AMD, Google, and Amazon are shipping capable alternative hardware that nobody uses because the software is too hard. We're breaking that moat. If we succeed, anyone will be able to train state-of-the-art models without thinking past their PyTorch code.
Full SF Tensor profile