Partcl

Partcl is ending the hardware lottery. We are developing the next generation of chip design automation tools with a focus on performance, scalability and productivity. We envision a future where hardware engineers benefit from advances in AI and believe the first place to start is with advanced optimization tools. We’re looking for engineers who think in terms of intermediate representations and passes — people who can design the data models that physical-design tools run on, not just use them. You should be able to move seamlessly between high-level IR design and low-level performance work, building the infrastructure that lets placement, routing, and timing engines operate at massive scale. At Partcl, we’re not here to play it safe - we’re here to win. We want people who wake up every day wanting to win too. If you are interested in solving massive-scale problems in physical AI, come join us. What you will do: Design the core intermediate representations that physical-design tools use to reason about chips Build compiler-like pipelines that lower, normalize, and transform design data across stages (netlist → floorplan → PnR → sign-off) Architect the physical-design data model as a first-class IR, not just a storage format Create high-performance loaders, serializers, and transformation passes for LEF/DEF, Liberty, SPEF, GDS Develop APIs that make analysis and optimization passes fast to write and reason about Own correctness invariants: name resolution, scoping, units, coordinate systems, legalizations, constraints Optimize for query latency, cache locality, memory layout, and parallel traversal Build validation and rewriting passes that catch inconsistencies and automatically repair design data Work directly with PnR, STA, and optimization engineers to co-design new IR features and passes Treat the database as a compiler backend, not a dumping ground Requirements: Strong background in compilers or IR design (LLVM, MLIR, TVM, CIRCT, or equivalent experience) Proficiency in Rust for low-level systems work; Python for tooling and pipelines Experience designing data structures for large graphs / sparse relations / geometric data Understanding of incremental computation, dependency tracking, and versioning of IR states Ability to reason about correctness, determinism, and reproducibility in complex toolchains Comfortable digging into massive designs and fixing pathological corner cases Nice to Have: Experience with CIRCT/MLIR or custom EDA IRs Prior work on static analysis, transformation passes, or compiler runtimes Fluency with physical-design file formats: LEF/DEF, Liberty, SDC, SPEF, GDS Deep familiarity with chip backend concepts: floorplanning, placement, routing, CTS, extraction Knowledge of timing models (CCS/LVF) and constraint propagation Experience with columnar or in-memory formats (Apache Arrow, Parquet, custom SOA layouts) Parallel compiler / GPU acceleration experience

Partcl is ending the hardware lottery. We are developing the next generation of chip design automation tools with a focus on performance, scalability and productivity. We envision a future where hardware engineers benefit from advances in AI and believe the first place to start is with advanced optimization tools. We are looking for extremely talented engineers who understand machine learning and systems at a deep level: engineers who can jump between performant architectures and CUDA kernels with ease, optimize inference pipelines, and develop systems that can grok terabytes of data in seconds. At Partcl, we’re not here to play it safe - we’re here to win. We want people who wake up every day wanting to win too. If you are interested in solving massive-scale problems in physical AI, come join us. What you will do: Explore new ML model architectures which give 1000x performance over existing methods for chip design. Architect and build end‑to‑end pipelines: high‑performance kernels, efficient file IO, training models, latency sensitive inference, CLI/UI layers. Talk to customers, deploy in their office, fix prod on the fly. Learn quickly. Requirements: Expert in PyTorch and CUDA programming. Deep understanding of systems - memory, latency, and performance tradeoffs. Experience designing, training and deploying custom models (a GPT wrapper does not count). Versatility: comfortable toggling between model architecture design, low‑level optimization and scaleable system design (N~>10M). Proficient with GPU profiling and performance analysis. Nice to Have: Exposure to chip design and electronic design automation (EDA). Expert in Reinforcement Learning Research in compilers, programming languages. Papers in respected conferences and journals. Experience with physics-driven ML.