
What the role involves
We’re looking for a key engineer with significant AI/ML + LLM experience to build AI-native core tools and models for agent-driven chip design workflows.
Who you are
- You are excited about transforming the way chips are built by the entire chip industry.
- You are resourceful, a self-starter, and care intensely about the quality of your work.
- You want to work at a scrappy startup that sets and meets aggressive goals.
- You want to own/drive core product and write/ship code every day.
- You want to work with our customers/users and translate their feedback into company/product direction.
- If this sounds like you, please apply to join the team!
- What you’ll do:
- Develop AI models, core tools, and infrastructure that ship to Fortune 500s and chip unicorns
- Make architectural decisions for key product features
- Translate user feedback into product updates/features
- Plan core product roadmap and strategy
Minimum requirements
- Highly skilled with Python, C++, PyTorch/torch
- Strong understanding of traditional ML models, LLMs, foundation models, and agents
- Experience building ML pipelines
- Experience fine-tuning and benchmarking LLMs/foundation models
- Excited about applying AI/ML techniques to chip design
- Good at shipping high-quality code quickly
- Resilient, data-driven, and works from first principles
Ideal requirements
- Have shipped product using LLMs, foundation models, and/or agentic workflows
- Experience with AWS SageMaker
Nice-to-have requirements
- Experience with AI/ML-driven chip EDA software tooling (either open-source or commercial tools)
- Experience with designing chips (either open-source or commercial designs)
Benefits
- Generous salary and equity package
- Full health/vision/dental/401k benefits
- Team meals
- —
- Apply to chat with the founders about the details!
About Silimate
We're building AI-native core tools & agent-driven workflows for frontend chip design. Today, Silimate is helping Fortune 500s and chip unicorns create & iterate to correct, optimized designs 40x faster. Our goal is to enable autonomous spec-to-design for silicon.
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